NanoSpeed to Provide Ultra-Fast Risk Checks to LSE

Nano-Risk FPGA allows users to submit their orders to ultra-fast risk checks, with a latency of less than half a microsecond. Orders are therefore redirected to the matching engine for execution after they have been cleared from any of the underlying security checks, such as quantity limits, value limits, and price diversion limits, which will determinate if an order is tradable or not.

The solution allows firms to access the market with low and deterministic latency, but also to check if their orders are in compliance with regulatory and operational requirements before they reach the market.

"Launching our high-speed LSE solution will now allow market participants to perform critical risk checks, such as fat-finger and client-specific checks (for direct market access), faster than ever before," says Sanjay Shah, CTO of NanoSpeed. "Because performing risk checks in software is very slow, our approach is to enable an institution to do the same thing, but on an FPGA. An institution can perform the vital calculations in under half a microsecond, which is 50-100 times faster than using software."

NanoSpeed recently implemented Nano-Risk FPGA on the Chicago Mercantile Exchange and is currently providing low-latency pre-trade checks on more than 30 exchanges globally, including Nasdaq and Eurex.